Cver - Verilog Simulator
cver [options][verilogfiles...]
Cver is a full 1995 IEEE P1364 standard Verilog simulator. This is
"GPL Cver", the GPL version.
The full documentation for Cver , please visit http://www.pragmatic-
c.com/gpl-cver
Pragmatic C Software Corp.
This manual page was written by NIIBE Yutaka <gniibe@fsij.org>, for the
Debian project (but may be used by others).